1. Field of the Invention
This invention relates to the manufacture of semiconductor devices, in particular, dynamic random access memories having self-aligned shallow trench isolation regions for isolating various transistors within a memory array.
2. Description of Related Art
In fabricating integrated circuits (ICs), the IC usually requires that individual active and passive circuit elements be electrically isolated from each other in a common semiconductor chip so that desired circuit connections may be made by patterned surface metallization with which the isolated circuit elements are in contact. Typically, a memory cell in an array of cells isolates the active circuit element from the passive circuit element, and itself must be isolated from adjacent cells and circuit elements. In addition to the memory cell array, many diverse techniques have been proposed over the years to electrically isolate the active and passive circuit elements including lithographic masking levels, junction isolation, dielectric isolation, and combinations thereof.
As the integration density of a Dynamic Random Access Memory (DRAM) steadily increases, including those having vertical trench capacitors, it becomes necessary to reduce the memory cell array size. In the fabrication of DRAMs, the memory cell size, or isolation region, is primarily determined by the minimum resolution dimension of a lithographic masking technique, the overlay tolerances between the different features of the memory cell size, and the layout of such features, while still maintaining the minimum required storage capacitance to reliably operate the DRAM. However, as the conventional integrated circuit DRAM cells are scaled to decreasingly smaller dimensions with advanced generations of memory products, the integration density of the memory array is increased, and as such, in order to meet the cell size and storage capacitance requirements, the associated process technology complexity of the DRAM cells increases, as well as the costs required to produce such modem high density memory arrays.
As IC dimensions get smaller and device densities increase, it becomes more difficult to efficiently and reliably isolate the active and passive circuit elements of the IC, as well as do so at a decreased cost. Prior art is aimed at using lithographic masking levels for isolating the active and passive circuit elements; however, the inclusion of lithographic masking levels in the fabrication of ICs introduces a variety of problems including processing complexities and fabrication errors, which may lead to inefficient and unreliable ICs, in turn leading to increased production costs. Thus, a need exists in the art to reduce the number of lithographic masking levels required for IC processing, thereby reducing the processing costs and complexity of the resultant chip.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method and assembly for eliminating conventional lithographic masking levels used to delineate the isolation region within a memory cell array during IC fabrication by forming a self-aligned shallow trench isolation structure in an IC array, preferably in a DRAM array.
Another object of the present invention is to provide a method and assembly for eliminating a fine feature size lithographic masking level in an array.
It is another object of the present invention to provide a method and assembly for reducing the complexity of the high-density memory product.
A further object of the invention is to provide a method and assembly for reducing fabrication costs in high-density memory products.
It is yet another object of the present invention to provide an efficient and reliable isolation process to isolate the smaller active and passive circuit elements of modern ICs.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, method of forming an isolation in a semiconductor substrate comprising providing a semiconductor substrate, forming a plurality of adjacent trenches, preferably vertical deep trenches, in the semiconductor substrate leaving adjacent segments of the semiconductor substrate between each of the adjacent trenches, and depositing a barrier layer in the plurality of adjacent trenches. Subsequently a portion of the barrier layer in each of the plurality of adjacent trenches is removed to expose portions of the adjacent segments of the semiconductor substrate, and such exposed portions of the adjacent segments of the semiconductor substrate are merged together to form a self-aligned shallow trench isolation.
Preferably, the semiconductor substrate is a silicon substrate having a pad dielectric layer thereover a surface of the silicon substrate. More preferably, the semiconductor substrate is a silicon substrate having a pad dielectric layer comprising a pad oxide layer followed by a pad nitride layer thereover the surface of the silicon substrate. The pad oxide layer may provided to a thickness ranging from about 1 to about 10 nm, while the pad nitride may be provided to a thickness ranging from about 50 to about 500 nm. In such an embodiment, the plurality of trenches formed in the substrate traverse through the pad oxide and pad nitride layers, stopping at a distance within the silicon substrate. Preferably the plurality of trenches are etched to a depth ranging from about 250 nm to about 10 xcexcm.
The barrier layer provided within the plurality of adjacent trenches may comprise an oxidation barrier layer. Preferably, the oxidation barrier layer is conformally deposited to at least coat the sidewalls and bottom surfaces of the plurality of trenches, more preferably to a thickness ranging from about 3 nm to about 30 nm. Subsequently a portion of the oxidation barrier layer within the plurality of trenches is recessed thereby exposing the portions of silicon substrate in a top portion of the plurality of trenches.
Preferably, the portions of the oxidation barrier layer are recessed by depositing a photoresist within remaining portions of the plurality of trenches having the oxidation barrier layer to at least fill such empty portions. A desired depth in the photoresist is then determined for recessing the oxidation barrier layer, preferably to a depth ranging from about 20 nm to about 2000 nm. Subsequently, the photoresist and the oxidation barrier layer within the plurality of trenches are etched stopping at the desired depth in the photoresist thereby recessing the oxidation barrier layer to the desired depth and exposing the portions of the adjacent segments of silicon substrate in a top portion of the plurality of adjacent trenches. Any remaining photoresist may then be removed.
Preferably, the exposed portions of the adjacent segments of the silicon substrate are then etched to form a plurality of thin sections of the exposed adjacent segments of the silicon substrate between each of the plurality of adjacent trenches. Preferably, the exposed portions of silicon substrate are etched using an etchant which selectively removes only the silicon substrate to form the plurality of thin sections of the exposed adjacent segments of the silicon substrate, including an etchant selected from the group consisting of a chlorine-containing etchant, KOH, and NH4OH. Preferably, the thin sections of the exposed adjacent segments of the silicon substrate between each of the plurality of adjacent trenches have a diameter ranging from about ⅕ to about xc2xd that of an original diameter of the exposed portions of the adjacent segments of the silicon substrate.
The plurality of thin sections of the exposed adjacent segments of the silicon substrate between each of the plurality of adjacent trenches are then merged together to form a self-aligned thermal oxide shallow trench isolation structure. Preferably, the self-aligned thermal oxide shallow trench isolation structure is formed by merging together the thin exposed portions of the semiconductor substrate, between vertical adjacent trenches, at least along a first row of selected ones of the plurality of trenches. More preferably, the self-aligned thermal oxide shallow trench isolation structure is formed by converting the thin portions of silicon substrate between adjacent trenches within the at least one row into the thermal oxide region by oxidation, such as by LOCOS, thereby forming a self-aligned silicon dioxide shallow trench isolation. Thus, the self-aligned thermal oxide shallow trench isolation structure of the instant invention isolates a first region of the semiconductor substrate on a first side of the at least one set of merged adjacent trenches from a second region of the semiconductor substrate on a second side of the at least one set of merged adjacent trenches.
After the merged self-aligned thermal oxide shallow trench isolation structure has been formed, remaining portions of the barrier layer in the plurality of adjacent trenches may be removed, a deep trench capacitor formed in each of the adjacent trenches, and subsequently a vertical transistor formed within the adjacent trenches to form a memory cell.
In another aspect, the present invention provides a self-aligned isolation structure in a semiconductor substrate comprising a semiconductor substrate, preferably a silicon substrate, having a plurality of adjacent trenches in the semiconductor substrate, and a self-aligned isolation structure in upper portions of selected ones of the plurality of trenches. The self-aligned isolation structure in the upper portions of selected ones of the plurality of trenches is merged portions of the semiconductor substrate along at least a first row of the selected ones of the plurality of adjacent trenches and is aligned as-formed to edges of the plurality of adjacent trenches. The self-aligned isolation structure isolates a first region of the semiconductor substrate from a second region of the semiconductor substrate.
In the present invention, the semiconductor substrate has a pad dielectric layer thereover a surface of the semiconductor substrate, preferably the pad dielectric layer comprises a pad oxide layer having a thickness ranging from about 1 to about 10 nm followed by a pad nitride layer having a thickness ranging from about 50 nm to about 500 nm. The plurality of trenches in the semiconductor substrate may have depths ranging from about 250 nm to about 10 xcexcm.
The isolation structure preferably comprises a thermal oxide region existing along the at least one row of selected ones of the plurality of trenches in upper portions of the semiconductor substrate. Preferably, wherein the semiconductor substrate comprises a silicon substrate, the thermal oxide region comprises a thermal silicon dioxide region existing along the at least one row of selected ones of the plurality of trenches in upper portions of the semiconductor substrate. In the present invention, the merged thermal oxide isolation structure along the at least one row of selected ones of the plurality of trenches in upper portions of the semiconductor substrate isolates a first region of the semiconductor substrate from a second region of the semiconductor substrate with the at least one row merged trenches.